I am a senior research fellow in EPCC at the University of Edinburgh, with interests and extensive experience in High Performance Computing (HPC). Working at the UK’s leading supercomputing centre, much of my research centres around the role that novel hardware can play in future supercomputers. Given that much of this novel hardware is highly energy efficient, it is likely that it will play a key role in moving our supercomputing workloads towards Net-Zero. I am specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively exploit such technologies without extensive hardware/architecture expertise. To this end, my research combines novel algorithmic techniques for this new hardware, programming language & library design, and compilers.
Research vision
The major motivation behind my research is that, for improved performance and energy efficiency, it should be possible to specialise the hardware we use for the computing task in hand. With a background in compilers and algorithm design, my focus is on how this can be supported automatically by the software stack and there are several strands to my work:
- Driven by specific kernels and applications, exploring and developing algorithmic techniques for novel hardware. For instance, understanding the most appropriate ways in which we can restructure Von-Neumann based CPU/GPU algorithms into a dataflow style for FPGAs and CGRAs.
- New programming constructs and paradigms for novel hardware that then feed into libraries and tools such as Domain Specific Languages (DSLs).
- Compiler techniques to enable automatic transformation and optimisation in supporting codes running on a variety of novel architectures, ideally with minimal or no input required from the programmer.
HPC Community
I am heavily involved in the global HPC community, for instance leading knowledge exchange for the £45m ExCALIBUR exascale software programme, chairing the RISC-V International HPC SIG, organising and chairing the RISC-V for HPC workshop series at ISC and SC, the UrgentHPC SC workshop series, organising the Interactive HPC ISC and SC workshop series, and have led numerous mini-symposia and miscellaneous workshops. I have served on the organising committee for several top HPC conferences, such as local chair for the compilers and runtimes track at Euro-Par22, and the PC of many other top HPC conferences including SC, ISC, IPDPS, and CCGrid. I have given numerous invited conference talks, for instance the opening keynote at the 30th Euromicro International conference on parallel, distributed, and network based processing about FPGAs for HPC in 2022.
Teaching and PhD supervision
I head up EPCC’s PhD programme and lead two MSc courses, the in-person and online parallel design patterns modules, and also teach on several other courses as part of EPCC’s MSc programmes in HPC and data science. I have supervised a large number of MSc dissertation students, and am the primary PhD supervisor of several PhD students. I am also an internal and external PhD examiner.