I am accepting PhD students, so if my research is of interest to you, then please get in touch! Due to the focus of my research, you must be a strong programmer, have a willingness and ability to pick up new technologies and techniques easily, and ideally have existing HPC experience.
Current PhD students
Mark Klaisoongnoen is exploring the role of FPGAs in accelerating quantitative finance workloads in an energy efficient manner. He is working with STAC research, the finance industry standard community body that develops numerous benchmarks for evaluating technologies for financial applications. Based upon Mark’s work he has been able to not only deliver significant energy reductions compared to CPUs or GPUs, but furthermore significantly outperform these technologies for specific quantitative finance benchmarks. This is because the performance of these are bound by aspects other than compute, and-so the bespoke nature of FPGAs where one can develop memory hierarchies and logic which is specialised for the problem in question is highly beneficial here. Mark is currently working on exploring the role of AMD Xilinx AI engines for quantitative finance workloads, which was an activity that he began during an internship with HPE.
Gabriel RodrÍguez Canal is researching enhancing the ecosystem for FPGAs to better support HPC code development. He has ported the Controller task-based model to AMD Xilinx and Intel FPGAs, leveraging partial reconfiguration to dynamically swap tasks in and out during execution and won the 2022 AMD Xilinx open hardware contest in the PhD category for this work. During an internship with HPE he developed Fortran-HLS, which couples the Flang frontend with the AMD Xilinx HLS backend, enabling direct Fortran HLS programming of FPGAs. Building upon this, he is now developing MLIR dialects and transformations to enable automatic dataflow optimisation of imperative codes, with the ultimate aim that serial codes can obtain high performance on FPGAs with no code changes required by the programmer.
David Kacs will be starting in October 2023 and researching compiler methods for programming the Cerebras CS-2. Integrating with MLIR, the objective will be to enable automatic transformation of codes to an algorithmic form that best suits the CS-2 architecture.
Graduated PhD students
Ludovic Capelli studied with me exploring bringing HPC methods and techniques to the vertex centric programming model. First developed by Google in 2010, vertex centric provides programmer productivity in graph based processing. However, until this work it typically required significant memory resources and performed poorly, with numerous frameworks compromising to optimise these features at the code of productivity. This work significantly enhanced vertex centric for both shared and distributed memory architectures, reducing memory usage by several orders of magnitude and Ludovic holds an (unofficial) world record for the largest vertex centric graph (750 billion edges) ever processed within a single node without requiring out-of-core computation. Developing a distributed version of his iPregel framework, called DiP, he was able to process graphs comprising 1.6 trillion edges using vertex centric. During his PhD Ludovic undertook internships with the National Institute of Informatics (NII) in Tokyo and Renault. He was also awarded a prestigious Huawei PhD fellowship and now works for EPCC as a teaching fellow.
Maurice Jamieson studied providing performance and programmer productivity on low SWaP micro-core architectures. These CPUs are typically very simple, have tiny memory spaces (e.g. 32KB or less) with no hardware caching support, and run bare-metal without an operating system. His work resulted in the development of a framework called Vipera for dynamic languages on these architectures, enabling at or near native C code performance for languages such as Python. Furthermore, using Vipera one is able to run codes of arbitrary sizes and datasets with a memory requirement of approximately 4KB, thus decoupling the requirements of an application from that of the hardware entirely from software. During the course of his research he also developed the Eithne benchmarking framework to enable easier measurement of codes on this class of architecture. Maurice now works for EPCC as a software architect.